1. Field of the Invention
This invention relates to an electro-luminescence display (ELD), and more particularly to an apparatus and method for driving an electro-luminescence panel wherein pixels existing in gate lines of a current driving type electro-luminescence panel are pre-charged to change a storage voltage of the pixel into the corresponding voltage within a limited scanning time.
2. Discussion of the Related Art
Recently, there have been developed various flat panel display devices reduced in weight and bulk that is capable of eliminating disadvantages of a cathode ray tube (CRT). Such flat panel display devices include a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP) and an electro-luminescence (EL) panel, etc.
Studies for heightening a display quality of the flat panel display device and for providing the flat panel display with a large-scale screen have been actively made. The EL panel in such display devices is a self-emission device capable of being emitted for itself. The EL panel excites a fluorescent material using carriers such as electrons and holes, etc. to display a video image. The EL panel has advantages in that a low direct current voltage driving is possible and a response speed is fast.
As shown in FIG. 1, such an EL panel includes gate lines GL1 to GLm and data lines DL1 to DLn arranged on a glass substrate 10 in such a manner to cross each other, and pixel elements PE arranged at intersections between the gate lines GL1 to GLm and the data lines DL1 to DLn. Each of the pixel elements PE is driven when gate signals on the gate lines GL1 to GLm are enabled, thereby generating a light corresponding to a magnitude of a pixel signal on the data line DL.
In order to drive such an EL panel, a gate driver 12 is connected to the gate lines GL1 to GLm, and a data driver 14 is connected to the data lines DL1 to DLn. The gate driver 12 sequentially drives the gate lines GL1 to GLm. The data driver 14 applies pixel signals, via the data lines DL1 to DLn, to the pixel elements PE.
As shown in FIG. 2, each of the pixel elements PE driven with the gate driver 12 and the data driver 14 consists of an EL cell OELD connected to a ground voltage line GND, and a cell driving circuit 16 for driving the EL cell OLED.
FIG. 2 is a detailed circuit diagram of the pixel element PE shown in FIG. 1, which includes a driving circuit arranged at an intersection between the gate line GL and the data line DL, that is, four TFT's T1, T2, T3 and T4.
Referring to FIG. 2, the pixel element PE includes an EL cell OLED connected to a ground voltage source GND, and an EL cell driving circuit 16 connected between the EL cell OLED and the data line DL.
The EL cell driving circuit 16 includes the first and second PMOS TFTs T1 and T2 connected to the EL cell OLED and the supply voltage line VDD, a third PMOS TFT T3 connected to the second PMOS TFT T2, the data line DL and the gate line GL to respond to a signal on the gate line GL, a fourth PMOS TFT T4 connected to the gate electrodes of the first and second PMOS TFT's T1 and T2, the gate line GL and the third PMOS TFT T3, and a capacitor Cst connected between the gate electrodes of the first and second PMOS TFTs T1 and T2 and the supply voltage line VDD.
In operation, when a low input signal is applied to the gate line GL as shown in FIG. 3, the third and fourth PMOS TFTs T3 and T4 are turned on. If so, a video signal with a certain amplitude inputted in synchronization with a scanning signal from the data line DL is charged into the capacitor Cst via the third and fourth PMOS TFTs T3 and T4. The capacitor Cst is connected to the gate electrodes of the first and second PMOS TFTs T1 and T2 and the supply voltage VDD to charge the video signal from the data line DL during a low voltage input period of the gate line GL.
The capacitor Cst holds the video signal applied from the data line DL and then charged during one frame interval. Because of this holding time, the capacitor Cst keeps an application of the video signal from the data line DL to the EL cell OLED. Further, such a structure must include the number of data lines DL receiving each picture signal in correspondence with an input of each video signal such as red(R), green(G) and blue(B) signals. After being held for one frame interval, the video signal charged in the capacitor Cst is applied to the EL cell OLED to display an image on the display panel.
However, the conventional EL panel driving apparatus has difficulty in charging and discharging the storage capacitor Cst by a driving current Id within a limited gate line scanning time to change the driving current Id into the corresponding voltage because a very small current is used as the driving current Id. Herein, the gate line scanning time means a time at which the third and fourth PMOS TFTs T3 and T4 have been simultaneously turned on.